1. Field of the Invention
The present invention relates to a sample-and-hold circuit, and more particularly to a sample-and-hold circuit which can sample and hold an input signal with higher accuracy.
2. Description of the Related Art
An example of a conventional sample-and-hold circuit using a diode bridge is shown in FIG. 1.
In FIG. 1, an input terminal DIN of the sample-and-hold circuit is connected to a node N11 of the diode bridge constituted by diodes 16 to 19. A node N12 of the diode bridge is connected to an input terminal of a voltage follower 12, as well as to one terminal of a holding capacitor 11. The other terminal of the capacitor 11 is grounded. An output terminal of the voltage follower 12 serves as an output terminal DOUT of the sample-and-hold circuit.
A collector of a PNP bipolar transistor 14 (hereinafter referred to as a PNP transistor), a collector of an NPN bipolar transistor 12 (hereinafter referred to as an NPN transistor), and a node N15 of the diode bridge are connected each other. Further, a collector of a PNP transistor 15, a collector of an NPN transistor 13, and a node N16 of the diode bridge are connected each other.
An emitter of the PNP transistor 14 is connected to an emitter of the PNP transistor 15, and a constant-current source I7 is connected between these emitters and a high-power-source-voltage terminal Vcc.
An emitter of the NPN transistor 12 is connected to an emitter of PNP transistor 13, and a constant-current source I8 is connected between these emitters and a low-power-source-voltage terminal GND.
Level shifters 22 and 24 are connected between a base of the PNP transistor 14 and the NPN transistor 12. A sampling clock signal CLK is supplied to a node N13 of the level shifters 22 and 24 through an input buffer 20 and an inverter 21.
Level shifters 23 and 25 are connected between a base of the PNP transistor 15 and a base of the NPN transistor 13. The sampling clock signal CLK is supplied to a node N14 of the level shifters 22 and 24.
An operation of the sample-and-hold circuit shown in FIG. 1 will now be described, with reference to a timing chart shown in FIG. 2. When the sampling clock signal CLK shown in FIG. 2 is at high level, which indicates a sampling, the nodes N13 and N14 are at low and high levels, respectively. For this reason, the PNP transistor 14 and the NPN transistor 13 become conductive, and thus nodes N15 and N16 assume high and low levels, respectively.
The diodes 16 to 19 are forward-biased, and the nodes N11 and N12 are both clamped to the same voltage level by the diodes 16 and 17. More specifically, the voltage level of the node N12 is the same as that of an input signal supplied to the input terminal DIN, as shown in FIG. 2. The holding capacitor 11 is charged or discharged on the basis of this voltage.
When the sampling clock signal CLK is at a low level which indicates a hold, the nodes N13 and N14 assume high and low levels, respectively. The NPN transistor 12 and the PNP transistor 15 become conductive, and thus the nodes N15 and N16 assume low and high levels, respectively. As a result, the diodes 16 to 19 are reverse-biased, for which reason the input signal is isolated from the node N12. Accordingly, the voltage level of the node N12 is retained at the voltage at sampling, due to the holding capacitor 11, and output through a voltage follower 12.
In the sample-and-hold circuit shown in FIG. 1, the NPN transistor 12 and the PNP transistor 15 are saturated at the hold time. Because of this, the time (acquisition time) required for changing from a hold mode to a sample mode is prolonged. Further, at the sampling time, a current flowing into the PNP transistor 14 and the NPN transistor 13 is shunted to two paths (a path of diodes 16 and 18 and a path of diodes 17 and 19). Thus, the holding capacitor 11 cannot be charged or discharged at high speed. Further, if the current is increased in order to charge the holding capacitor 11 at high speed, the current flowing through the diodes 16 and 18 will also be increased, resulting in increased power dissipation.
Moreover, when the mode is changed from the sample mode to the hold mode, the change of voltages at the nodes N15 and N16 changes the voltage of node N12 through a coupling due to the junction capacitance of diodes 17 and 19. This phenomenon is known as "feedthrough". As shown in FIG. 2, when the mode is changed from the sample mode to the hold mode, the voltage-level change amount of each voltage level of the nodes N15 and.16 depends on the level of an input signal. As a result, the feed through differs, depending on the level of the input signal, resulting in degraded sampling accuracy.
The sample-and-hold circuit disclosed in this document is arranged as shown in FIG. 3. In the circuit shown in FIG. 3, when the clock signal CLKA is at a high level, transistors 52 and 50 are turned on and transistors 51 and 53 are turned off. Accordingly, the diodes 54 and 55 are forward-biased and diodes 56 and 57 are reverse-biased. If the forward voltage (VF) of the emitter-base junction of the transistor 50 is identical to the forward voltage of the diode 54, a voltage the same as that of the input signal VIN is applied to the hold capacitor 58. On the other hand, the hold capacitor 59 is electrically isolated from the input signal VIN, and the signal level thereof is maintained.
When clock signal CLKA is at a low level, transistors 52 and 50 are turned off and transistors 53 and 51 are turned on. As a result, diodes 54 and 55 are reverse-biased and diodes 56 and 57 are forward-biased. Accordingly, a voltage the same as that of the input signal VIN is applied to the hold capacitor 59, and hold capacitor 58 is isolated from the input signal VIN.
The sample-and-hold circuit shown in FIG. 3 eliminates the problem associated with the circuits shown in FIG. 1; i.e. the problem wherein the bias current is divided by the diode bridges and thus the charge and discharge of the hold capacitor is delayed. However, the current for charging or discharging the hold capacitors 58 and 59 is determined by the bias current IC, and the maximum charge or discharge current of the hold capacitors 58 and 59 is 2.IC/3 at most. Thus, a higher-speed charging and discharging operation requires a larger bias current, resulting in increased power consumption.